Multiprocessing digital signal processors generally use a hierarchical or peer-to-peer processor array. Unfortunately, when new processing elements are added to the digital signal processors, a rewrite of pre-existing code is often required. Moreover, the software that runs the digital signal processors is dependent on hardware timing and is thus not portable across different silicon process technologies. As a result, binary or assembly code written on one version of these processors may not be portable to other versions that have different processing elements. One technique for implementing multiprocessing digital signal processors is the use of a data driven architecture.
In contrast to a data driven architecture, processors currently in widespread use are developed according to so-called Von Newman logic. According to Von Newman logic, processors sequentially process instructions, one at a time. In addition, Von Newman processors operate using a clock to control data input/output (I/O) and execute programs one instruction at a time. As a result, increasing processing speed requires an increase in clock frequency that leads increased power consumption.
In other words, the functioning of a microprocessor requires synchronization of data transfer and writing data to memory. One method of synchronizing is to tie all circuits to a common signal called a clock signal. Unfortunately, because the majority of internal circuitry is tied to this clock, the internal circuitry does not perform well when processing data intensive applications. In contrast, data driven architectures utilize processors that process without regard to data sequence and only when data is available. Accordingly, because multiple programs are read whenever multiple data is input, data processing is performed in parallel within data driven architectures.
Hardware accelerators are designed to accelerate commonly used data processing functions or operations to improve and speed up processing. In a data driven architecture, several hardware accelerators may be embodied in digital processing units to improve data processing performance. Unfortunately, the number of hardware accelerators that can be controlled within a digital processing unit is limited by several factors such as addressing of the hardware accelerators. As a result of these limitations, the number of hardware accelerators is limited to a few very large and complex hardware accelerators. This desire conflicts with the desire to have several smaller and simpler hardware accelerators within the digital processing units of the data driven architecture.